1. Field of the Invention
The present invention relates to an accelerator circuit for an image processing apparatus as well as to the image processing apparatus including the accelerator circuit.
2. Description of the Related Art
Processing an image using a dedicated hardware device generally reduces processing time as compared with processing the image using software executed by a general-purpose processor. With this in view, an accelerator circuit, which is a dedicated hardware device that performs a predetermined simple arithmetic operation, is used in some cases. In particular, use of an accelerator circuit yields considerable reduction in processing time when two-dimensional (hereinafter, “2D”) filtering is to be applied to image data.
According to a technique disclosed in Japanese Laid-open Patent Application No. 2002-211050, a printer, which is an example of an image output apparatus, includes a CPU (central processing unit) that performs drawing processing using software and a drawing accelerator that performs high-speed drawing processing using hardware, for example. The CPU interprets a drawing command based on an output command fed from a host computer and causes the drawing accelerator to perform a drawing operation on a target area of the drawing command. The drawing operation is performed block by block from, for example, the first block of the target area. Simultaneously, the CPU performs the drawing operation on the target area of the drawing command block by block from, for example, the last block of the target area. The CPU completes the operation of the drawing command when a sum of the areas on which the operation of the drawing command is performed respectively by the drawing accelerator and by the CPU becomes equal to the target area of the drawing command. This technique allows providing an inexpensive image output apparatus, such as a printer, that outputs images by performing drawing operations simply and at high speeds.
An image processing apparatus according to Japanese Laid-open Patent Application No. 2013-239120 includes one or more processors that perform arithmetic operation on image data using software, one or more hardware accelerators that perform predetermined arithmetic operation on the image data, a memory unit, and a buffer control unit that controls writes and reads to and from the memory unit. Storage area of the memory unit is physically divided into buffer spaces, the number of which is equal to or greater than ((the number of the processors)+(the number of the hardware accelerators)−1). The buffer control unit controls a write and a read of image data to and from a corresponding buffer space of the buffer spaces in accordance with an access from each of the processors and the hardware accelerators. This configuration provides an image processing apparatus including an image processing circuit capable of changing arithmetic operations related to image processing flexibly as desired without increasing in a circuit size.
Some type of conventional accelerator circuits processes image data fed from an entity external to an image processing apparatus and passes the processed image data to a main memory, but some other type processes image data transferred from a main memory by DMA (direct memory access) transfer and returns the processed image data to the main memory. An accelerator circuit of the former type is incapable of processing image data stored in a main memory. Accordingly, to process both image data fed from an entity external to the image processing apparatus and image data in the main memory, two types of accelerator circuits are required to be used in parallel, which results in an increase in circuit size. In particular, an accelerator circuit serving as a 2D filter has a problem that as many multipliers as 2D spaces for high-speed processing are required, thereby causing a particular increase in a circuit size.
For reducing a circuit size, selecting by a selector one of image data fed from an entity external to the image processing apparatus and image data in the main memory, and feeding the selected image data to a single accelerator circuit may be performed. However, there exists a time delay since switching the selector is performed until an arithmetic operation is enabled (in a case of 2D filtering, until data is written to a 2D register). If image data fed to the accelerator circuit is frequently switched, a time delay that occurs each switching increases a period of time during which arithmetic operation of image data is not performed.
Under the circumstances, there is a need for an accelerator circuit capable of reducing an increase in a period of time during which arithmetic operation of image data is not performed and reducing a circuit size.
It is an object of the present invention to at least partially solve the problem in the conventional technology.